OIS1=B_0x0, TI1S=B_0x0, MMS=B_0x0, CCUS=B_0x0, OIS1N=B_0x0, CCDS=B_0x0, MMS2=B_0x0, CCPC=B_0x0
TIM1 control register 2
| CCPC | Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 (B_0x0): CCxE, CCxNE and OCxM bits are not preloaded 1 (B_0x1): CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). |
| CCUS | Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 0 (B_0x0): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1 (B_0x1): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI |
| CCDS | Capture/compare DMA selection 0 (B_0x0): CCx DMA request sent when CCx event occurs 1 (B_0x1): CCx DMA requests sent when update event occurs |
| MMS | Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 1 (B_0x1): Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 2 (B_0x2): Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 3 (B_0x3): Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 4 (B_0x4): Compare - OC1REFC signal is used as trigger output (TRGO) 5 (B_0x5): Compare - OC2REFC signal is used as trigger output (TRGO) 6 (B_0x6): Compare - OC3REFC signal is used as trigger output (TRGO) 7 (B_0x7): Compare - OC4REFC signal is used as trigger output (TRGO) |
| TI1S | TI1 selection 0 (B_0x0): The TIMx_CH1 pin is connected to TI1 input 1 (B_0x1): The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) |
| OIS1 | Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1 (B_0x1): OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 |
| OIS1N | Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): OC1N=0 after a dead-time when MOE=0 1 (B_0x1): OC1N=1 after a dead-time when MOE=0 |
| OIS2 | Output Idle state 2 (OC2 output) Refer to OIS1 bit |
| OIS2N | Output Idle state 2 (OC2N output) Refer to OIS1N bit |
| OIS3 | Output Idle state 3 (OC3 output) Refer to OIS1 bit |
| OIS3N | Output Idle state 3 (OC3N output) Refer to OIS1N bit |
| OIS4 | Output Idle state 4 (OC4 output) Refer to OIS1 bit |
| OIS5 | Output Idle state 5 (OC5 output) Refer to OIS1 bit |
| OIS6 | Output Idle state 6 (OC6 output) Refer to OIS1 bit |
| MMS2 | Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset. 1 (B_0x1): Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register). 2 (B_0x2): Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer. 3 (B_0x3): Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2). 4 (B_0x4): Compare - OC1REFC signal is used as trigger output (TRGO2) 5 (B_0x5): Compare - OC2REFC signal is used as trigger output (TRGO2) 6 (B_0x6): Compare - OC3REFC signal is used as trigger output (TRGO2) 7 (B_0x7): Compare - OC4REFC signal is used as trigger output (TRGO2) 8 (B_0x8): Compare - OC5REFC signal is used as trigger output (TRGO2) 9 (B_0x9): Compare - OC6REFC signal is used as trigger output (TRGO2) 10 (B_0xA): Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2 11 (B_0xB): Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2 12 (B_0xC): Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2 13 (B_0xD): Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2 14 (B_0xE): Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2 15 (B_0xF): Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2 |