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STMicroelectronics /STM32U083 /TIM15 /TIM15_AF1

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Interpret as TIM15_AF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BKINE 0 (B_0x0)BKCMP1E 0 (B_0x0)BKCMP2E 0 (B_0x0)BKINP 0 (B_0x0)BKCMP1P 0 (B_0x0)BKCMP2P

BKCMP2P=B_0x0, BKINE=B_0x0, BKINP=B_0x0, BKCMP1P=B_0x0, BKCMP1E=B_0x0, BKCMP2E=B_0x0

Description

TIM15 alternate register 1

Fields

BKINE

BRK BKIN input enable

0 (B_0x0): BKIN input disabled

1 (B_0x1): BKIN input enabled
BKCMP1E

BRK COMP1 enable

0 (B_0x0): COMP1 input disabled

1 (B_0x1): COMP1 input enabled
BKCMP2E

BRK COMP2 enable

0 (B_0x0): COMP2 input disabled

1 (B_0x1): COMP2 input enabled
BKINP

BRK BKIN input polarity

0 (B_0x0): BKIN input is active low

1 (B_0x1): BKIN input is active high
BKCMP1P

BRK COMP1 input polarity

0 (B_0x0): COMP1 input is active low

1 (B_0x1): COMP1 input is active high
BKCMP2P

BRK COMP2 input polarity

0 (B_0x0): COMP2 input is active low

1 (B_0x1): COMP2 input is active high

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data