TS=B_0x0, MSM=B_0x0, SMS=B_0x0
TIM15 slave mode control register
| SMS | SMS[2:0]: Slave mode selection 0 (B_0x0): Slave mode disabled - if CEN = 1’ then the prescaler is clocked directly by the internal clock. 4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. 6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). 7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. |
| TS | TS[2:0]: Trigger selection 0 (B_0x0): Internal Trigger 0 (ITR0) 1 (B_0x1): Internal Trigger 1 (ITR1) 2 (B_0x2): Internal Trigger 2 (ITR2) 3 (B_0x3): Internal Trigger 3 (ITR3) 4 (B_0x4): TI1 Edge Detector (TI1F_ED) 5 (B_0x5): Filtered Timer Input 1 (TI1FP1) 6 (B_0x6): Filtered Timer Input 2 (TI2FP2) |
| MSM | Master/slave mode 0 (B_0x0): No action 1 (B_0x1): The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). |
| SMS_1 | SMS[3] |
| TS_1 | TS[4:3] |