STMicroelectronics /STM32U083 /TIM16 /TIM16_CCMR1_ALTERNATE1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIM16_CCMR1_ALTERNATE1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CC1S 0 (B_0x0)OC1FE 0 (B_0x0)OC1PE 0 (B_0x0)OC1M0 (OC1M_1)OC1M_1

OC1PE=B_0x0, OC1FE=B_0x0, OC1M=B_0x0, CC1S=B_0x0

Description

TIM16 capture/compare mode register 1

Fields

CC1S

Capture/Compare 1 selection

0 (B_0x0): CC1 channel is configured as output

1 (B_0x1): CC1 channel is configured as input, IC1 is mapped on TI1

OC1FE

Output Compare 1 fast enable

0 (B_0x0): CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON.

1 (B_0x1): An active edge on the trigger input acts like a compare match on CC1 output.

OC1PE

Output Compare 1 preload enable

0 (B_0x0): Preload register on TIMx_CCR1 disabled.

1 (B_0x1): Preload register on TIMx_CCR1 enabled.

OC1M

OC1M[2:0]: Output Compare 1 mode

0 (B_0x0): Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.

1 (B_0x1): Set channel 1 to active level on match.

2 (B_0x2): Set channel 1 to inactive level on match.

3 (B_0x3): Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

4 (B_0x4): Force inactive level - OC1REF is forced low.

5 (B_0x5): Force active level - OC1REF is forced high.

6 (B_0x6): PWM mode 1 - Channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive.

7 (B_0x7): PWM mode 2 - Channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active.

OC1M_1

OC1M[3]

Links

()