TS=B_0x0, ETPS=B_0x0, OCCS=B_0x0, ECE=B_0x0, MSM=B_0x0, SMS=B_0x0, ETP=B_0x0, ETF=B_0x0
TIM2 slave mode control register
| SMS | SMS[2:0]: Slave mode selection 0 (B_0x0): Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. 1 (B_0x1): Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 2 (B_0x2): Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 3 (B_0x3): Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. 6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). 7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. |
| OCCS | OCREF clear selection 0 (B_0x0): OCREF_CLR_INT is connected to COMP1 or COMP2 output depending on TIMx_OR1. 1 (B_0x1): OCREF_CLR_INT is connected to ETRF |
| TS | TS[2:0]: Trigger selection 0 (B_0x0): Internal Trigger 0 (ITR0) 1 (B_0x1): Internal Trigger 1 (ITR1) 2 (B_0x2): Internal Trigger 2 (ITR2) 3 (B_0x3): Internal Trigger 3 (ITR3) 4 (B_0x4): TI1 Edge Detector (TI1F_ED) 5 (B_0x5): Filtered Timer Input 1 (TI1FP1) 6 (B_0x6): Filtered Timer Input 2 (TI2FP2) 7 (B_0x7): External Trigger input (ETRF) |
| MSM | Master/Slave mode 0 (B_0x0): No action 1 (B_0x1): The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). |
| ETF | External trigger filter 0 (B_0x0): No filter, sampling is done at fless thansub>DTSless than/sub> 1 (B_0x1): fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=2 2 (B_0x2): fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=4 3 (B_0x3): fless thansub>SAMPLINGless than/sub>=fless thansub>CK_INTless than/sub>, N=8 4 (B_0x4): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 5 (B_0x5): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 6 (B_0x6): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 7 (B_0x7): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 8 (B_0x8): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 9 (B_0x9): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 10 (B_0xA): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 11 (B_0xB): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 12 (B_0xC): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 13 (B_0xD): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 14 (B_0xE): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 15 (B_0xF): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 |
| ETPS | External trigger prescaler 0 (B_0x0): Prescaler OFF 1 (B_0x1): ETRP frequency divided by 2 2 (B_0x2): ETRP frequency divided by 4 3 (B_0x3): ETRP frequency divided by 8 |
| ECE | External clock enable 0 (B_0x0): External clock mode 2 disabled 1 (B_0x1): External clock mode 2 enabled. |
| ETP | External trigger polarity 0 (B_0x0): ETR is non-inverted, active at high level or rising edge 1 (B_0x1): ETR is inverted, active at low level or falling edge |
| SMS_1 | SMS[3] |
| TS_1 | TS[4:3] |