Regviz

STMicroelectronics /STM32U083 /TIM3 /TIM3_CCMR2_ALTERNATE1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIM3_CCMR2_ALTERNATE1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32U031/TIM3/TIM3_CCMR2_ALTERNATE1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CC3S 0 (OC3FE)OC3FE 0 (OC3PE)OC3PE 0OC3M0 (OC3CE)OC3CE 0 (B_0x0)CC4S 0 (OC4FE)OC4FE 0 (OC4PE)OC4PE 0OC4M0 (OC4CE)OC4CE 0 (OC3M_1)OC3M_1 0 (OC4M_1)OC4M_1

CC3S=B_0x0, CC4S=B_0x0

Description

TIM3 capture/compare mode register 2

Fields

CC3S

Capture/Compare 3 selection

0 (B_0x0): CC3 channel is configured as output

1 (B_0x1): CC3 channel is configured as input, IC3 is mapped on TI3

2 (B_0x2): CC3 channel is configured as input, IC3 is mapped on TI4

3 (B_0x3): CC3 channel is configured as input, IC3 is mapped on TRC.
OC3FE

Output compare 3 fast enable
OC3PE

Output compare 3 preload enable
OC3M

OC3M[2:0]: Output compare 3 mode
OC3CE

Output compare 3 clear enable
CC4S

Capture/Compare 4 selection

0 (B_0x0): CC4 channel is configured as output

1 (B_0x1): CC4 channel is configured as input, IC4 is mapped on TI4

2 (B_0x2): CC4 channel is configured as input, IC4 is mapped on TI3

3 (B_0x3): CC4 channel is configured as input, IC4 is mapped on TRC.
OC4FE

Output compare 4 fast enable
OC4PE

Output compare 4 preload enable
OC4M

OC4M[2:0]: Output compare 4 mode
OC4CE

Output compare 4 clear enable
OC3M_1

OC3M[3]
OC4M_1

OC4M[3]

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data