CTPL=B_0x0, TSCE=B_0x0, PGPSC=B_0x0, SSD=B_0x0, MCV=B_0x0, SSE=B_0x0, SYNCPOL=B_0x0, START=B_0x0, SSPSC=B_0x0, CTPH=B_0x0, IODEF=B_0x0, AM=B_0x0
TSC control register
| TSCE | Touch sensing controller enable This bit is set and cleared by software to enable/disable the touch sensing controller. Note: When the touch sensing controller is disabled, TSC registers settings have no effect. 0 (B_0x0): Touch sensing controller disabled 1 (B_0x1): Touch sensing controller enabled |
| START | Start a new acquisition This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the acquisition is complete or by software to cancel the ongoing acquisition. 0 (B_0x0): Acquisition not started 1 (B_0x1): Start a new acquisition |
| AM | Acquisition mode This bit is set and cleared by software to select the acquisition mode. Note: This bit must not be modified when an acquisition is ongoing. 0 (B_0x0): Normal acquisition mode (acquisition starts as soon as START bit is set) 1 (B_0x1): Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) |
| SYNCPOL | Synchronization pin polarity This bit is set and cleared by software to select the polarity of the synchronization input pin. 0 (B_0x0): Falling edge only 1 (B_0x1): Rising edge and high level |
| IODEF | I/O Default mode This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when there is no ongoing acquisition. When there is an ongoing acquisition, it defines the configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O). Note: This bit must not be modified when an acquisition is ongoing. 0 (B_0x0): I/Os are forced to output push-pull low 1 (B_0x1): I/Os are in input floating |
| MCV | Max count value These bits are set and cleared by software. They define the maximum number of charge transfer pulses that can be generated before a max count error is generated. Note: These bits must not be modified when an acquisition is ongoing. 0 (B_0x0): 255 1 (B_0x1): 511 2 (B_0x2): 1023 3 (B_0x3): 2047 4 (B_0x4): 4095 5 (B_0x5): 8191 6 (B_0x6): 16383 |
| PGPSC | Pulse generator prescaler These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). Note: These bits must not be modified when an acquisition is ongoing. Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. 0 (B_0x0): fHCLK 1 (B_0x1): fHCLK /2 2 (B_0x2): fHCLK /4 3 (B_0x3): fHCLK /8 4 (B_0x4): fHCLK /16 5 (B_0x5): fHCLK /32 6 (B_0x6): fHCLK /64 7 (B_0x7): fHCLK /128 |
| SSPSC | Spread spectrum prescaler This bit is set and cleared by software. It selects the AHB clock divider used to generate the spread spectrum clock (SSCLK). Note: This bit must not be modified when an acquisition is ongoing. 0 (B_0x0): fHCLK 1 (B_0x1): fHCLK /2 |
| SSE | Spread spectrum enable This bit is set and cleared by software to enable/disable the spread spectrum feature. Note: This bit must not be modified when an acquisition is ongoing. 0 (B_0x0): Spread spectrum disabled 1 (B_0x1): Spread spectrum enabled |
| SSD | Spread spectrum deviation These bits are set and cleared by software. They define the spread spectrum deviation which consists in adding a variable number of periods of the SSCLK clock to the charge transfer pulse high state. … Note: These bits must not be modified when an acquisition is ongoing. 0 (B_0x0): 1x tSSCLK 1 (B_0x1): 2x tSSCLK 127 (B_0x7F): 128x tSSCLK |
| CTPL | Charge transfer pulse low These bits are set and cleared by software. They define the duration of the low state of the charge transfer pulse (transfer of charge from CX to CS). … Note: These bits must not be modified when an acquisition is ongoing. Note: Some configurations are forbidden. Refer to the Section119.4.4: Charge transfer acquisition sequence for details. 0 (B_0x0): 1x tPGCLK 1 (B_0x1): 2x tPGCLK 15 (B_0xF): 16x tPGCLK |
| CTPH | Charge transfer pulse high These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of CX). … Note: These bits must not be modified when an acquisition is ongoing. 0 (B_0x0): 1x tPGCLK 1 (B_0x1): 2x tPGCLK 15 (B_0xF): 16x tPGCLK |