SRAMBUSY=B_0x0, DED=B_0x0, SEDC=B_0x0
| SEDC | ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers. 0 (B_0x0): No single error 1 (B_0x1): Single error detected and corrected |
| DED | ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers. 0 (B_0x0): No double error 1 (B_0x1): Double error detected |
| SRAMBUSY | SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or readout protection regression. Refer to . 0 (B_0x0): No erase operation on going 1 (B_0x1): Erase operation on going |