Regviz

STMicroelectronics /STM32U535 /RCC /RCC_AHB2ENR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_AHB2ENR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32U599/RCC/RCC_AHB2ENR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)FSMCEN 0 (B_0x0)OCTOSPI1EN 0 (B_0x0)OCTOSPI2EN 0 (B_0x0)HSPI1EN 0 (B_0x0)SRAM6EN 0 (B_0x0)SRAM5EN

SRAM6EN=B_0x0, HSPI1EN=B_0x0, OCTOSPI2EN=B_0x0, SRAM5EN=B_0x0, OCTOSPI1EN=B_0x0, FSMCEN=B_0x0

Description

RCC AHB2 peripheral clock enable register 2

Fields

FSMCEN

FSMC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): FSMC clock disabled

1 (B_0x1): FSMC clock enabled
OCTOSPI1EN

OCTOSPI1 clock enable This bit is set and cleared by software.

0 (B_0x0): OCTOSPI1 clock disabled

1 (B_0x1): OCTOSPI1 clock enabled
OCTOSPI2EN

OCTOSPI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): OCTOSPI2 clock disabled

1 (B_0x1): OCTOSPI2 clock enabled
HSPI1EN

HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): HSPI1 clock disabled

1 (B_0x1): HSPI1 clock enabled
SRAM6EN

SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): SRAM6 clock disabled

1 (B_0x1): SRAM6 clock enabled
SRAM5EN

SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): SRAM5 clock disabled

1 (B_0x1): SRAM5 clock enabled

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data