LPTIM2RST=B_0x0, FDCAN1RST=B_0x0, I2C6RST=B_0x0, UCPD1RST=B_0x0, I2C4RST=B_0x0, I2C5RST=B_0x0
RCC APB1 peripheral reset register 2
| I2C4RST | I2C4 reset This bit is set and cleared by software 0 (B_0x0): No effect 1 (B_0x1): Reset the I2C4. |
| LPTIM2RST | LPTIM2 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the LPTIM2. |
| I2C5RST | I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the I2C5. |
| I2C6RST | I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the I2C6. |
| FDCAN1RST | FDCAN1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the FDCAN1. |
| UCPD1RST | UCPD1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the UCPD1. |