PLL2QEN=B_0x0, PLL2M=B_0x0, PLL2SRC=B_0x0, PLL2PEN=B_0x0, PLL2REN=B_0x0
RCC PLL2 configuration register
| PLL2SRC | PLL2 entry clock source This bitfield is set and cleared by software to select PLL2 clock source. It can be written only when the PLL2 is disabled. To save power, when no PLL2 is used, this bitfield value must be�zero. 0 (B_0x0): No clock sent to PLL2 1 (B_0x1): MSIS clock selected as PLL2 clock entry 2 (B_0x2): HSI16 clock selected as PLL2 clock entry 3 (B_0x3): HSE clock selected as PLL2 clock entry |
| PLL2RGE | PLL2 input frequency range This bitfield is set and reset by software to select the proper reference frequency range used for�PLL2. It must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz |
| PLL2FRACEN | PLL2 fractional latch enable This bit is set and reset by software to latch the content of PLL2FRACN in the ΣΔ modulator. In order to latch the PLL2FRACN value into the ΣΔ modulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see PLL initialization phase for details). |
| PLL2M | Prescaler for PLL2 This bitfield is set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). … 0 (B_0x0): division by 1 (bypass) 1 (B_0x1): division by 2 2 (B_0x2): division by 3 15 (B_0xF): division by 16 |
| PLL2PEN | PLL2 DIVP divider output enable This bit is set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when pll2_p_ck is not used. 0 (B_0x0): pll2_p_ck output disabled 1 (B_0x1): pll2_p_ck output enabled |
| PLL2QEN | PLL2 DIVQ divider output enable This bit is set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when pll2_q_ck is not used. 0 (B_0x0): pll2_q_ck output disabled 1 (B_0x1): pll2_q_ck output enabled |
| PLL2REN | PLL2 DIVR divider output enable This bit is set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when pll2_r_ck is not used. 0 (B_0x0): pll2_r_ck output disabled 1 (B_0x1): pll2_r_ck output enabled |