PLL2Q=B_0x0, PLL2R=B_0x0, PLL2P=B_0x0
RCC PLL2 dividers configuration register
| PLL2N | Multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). … … Others: reserved VCO output frequency = Fref2_ck x PLL2N, when fractional value 0 has been loaded in PLL2FRACN, with: PLL2N between 4 and 512 input frequency Fref2_ck between 1MHz and 16MHz 3 (B_0x003): PLL2N = 4 4 (B_0x004): PLL2N = 5 5 (B_0x005): PLL2N = 6 128 (B_0x080): PLL2N = 129 (default after reset) 511 (B_0x1FF): PLL2N = 512 |
| PLL2P | PLL2 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll2_p_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). … 0 (B_0x0): pll2_p_ck = vco2_ck 1 (B_0x1): pll2_p_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_p_ck = vco2_ck / 3 3 (B_0x3): pll2_p_ck = vco2_ck / 4 127 (B_0x7F): pll2_p_ck = vco2_ck / 128 |
| PLL2Q | PLL2 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll2_q_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). … 0 (B_0x0): pll2_q_ck = vco2_ck 1 (B_0x1): pll2_q_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_q_ck = vco2_ck / 3 3 (B_0x3): pll2_q_ck = vco2_ck / 4 127 (B_0x7F): pll2_q_ck = vco2_ck / 128 |
| PLL2R | PLL2 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll2_r_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). … 0 (B_0x0): pll2_r_ck = vco2_ck 1 (B_0x1): pll2_r_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_r_ck = vco2_ck / 3 3 (B_0x3): pll2_r_ck = vco2_ck / 4 127 (B_0x7F): pll2_r_ck = vco2_ck / 128 |