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STMicroelectronics /STM32U545 /ADF1 /ADF_DLY0CR

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Interpret as ADF_DLY0CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SKPDLY0 (SKPBF)SKPBF

Description

ADF delay control register 0

Fields

SKPDLY

Delay to apply to a bitstream
SKPBF

Skip busy flag

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data