LATENCY=B_0x0, PRFTEN=B_0x0, SLEEP_PD=B_0x0, PDREQ2=B_0x0, PDREQ1=B_0x0, LPM=B_0x0
FLASH access control register
| LATENCY | Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. … 0 (B_0x0): Zero wait state 1 (B_0x1): One wait state 2 (B_0x2): Two wait states 15 (B_0xF): Fifteen wait states |
| PRFTEN | Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory. 0 (B_0x0): Prefetch disabled 1 (B_0x1): Prefetch enabled |
| LPM | Low-power read mode This bit puts the Flash memory in low-power read mode. 0 (B_0x0): Flash not in low-power read mode 1 (B_0x1): Flash in low-power read mode |
| PDREQ1 | Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked. 0 (B_0x0): No request for bank 1 to enter power-down mode 1 (B_0x1): Bank 1 requested to enter power-down mode |
| PDREQ2 | Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked. 0 (B_0x0): No request for bank 2 to enter power-down mode 1 (B_0x1): Bank 2 requested to enter power-down mode |
| SLEEP_PD | Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. The Flash must not be put in power-down while a program or an erase operation is on-going. 0 (B_0x0): Flash in Idle mode during Sleep mode 1 (B_0x1): Flash in power-down mode during Sleep mode |