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STMicroelectronics /STM32U545 /GTZC1_TZSC /TZSC_MPCWM4ACFGR

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Interpret as TZSC_MPCWM4ACFGR

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31282724232019161512118743000000000000000000000000000000000000000000 (SREN)SREN0 (SRLOCK)SRLOCK0 (SEC)SEC0 (PRIV)PRIV

Description

TZSC memory 4 sub-region A watermark configuration register

Fields

SREN

Sub-region enable
SRLOCK

Sub-region lock
SEC

Secure sub-region
PRIV

Privileged sub-region

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data