ADC12RST=B_0x0, HASHRST=B_0x0, OTGRST=B_0x0, GPIOHRST=B_0x0, SDMMC1RST=B_0x0, GPIOIRST=B_0x0, DCMI_PSSIRST=B_0x0, GPIOFRST=B_0x0, AESRST=B_0x0, GPIOJRST=B_0x0, PKARST=B_0x0, RNGRST=B_0x0, SDMMC2RST=B_0x0, GPIOGRST=B_0x0, GPIODRST=B_0x0, GPIOBRST=B_0x0, GPIOERST=B_0x0, OTFDEC2RST=B_0x0, OTFDEC1RST=B_0x0, GPIOCRST=B_0x0, GPIOARST=B_0x0, SAESRST=B_0x0, OCTOSPIMRST=B_0x0
RCC AHB2 peripheral reset register 1
| GPIOARST | I/O port A reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port A. |
| GPIOBRST | I/O port B reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port B. |
| GPIOCRST | I/O port C reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port C. |
| GPIODRST | I/O port D reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port D. |
| GPIOERST | I/O port E reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port E. |
| GPIOFRST | I/O port F reset This bit is set and cleared by software. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset I/O port F |
| GPIOGRST | I/O port G reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port G. |
| GPIOHRST | I/O port H reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port H. |
| GPIOIRST | I/O port I reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port .I |
| GPIOJRST | I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the I/O port J. |
| ADC12RST | ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. 0 (B_0x0): No effect 1 (B_0x1): Reset the ADC1 and ADC2. |
| DCMI_PSSIRST | DCMI and PSSI reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the DCMI and PSSI. |
| OTGRST | OTG_FS or OTG_HS reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the OTG_FS or OTG_HS. |
| AESRST | AES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the AES. |
| HASHRST | HASH reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the HASH. |
| RNGRST | RNG reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the RNG. |
| PKARST | PKA reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the PKA. |
| SAESRST | SAES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the SAES. |
| OCTOSPIMRST | OCTOSPIM reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the OCTOSPIM. |
| OTFDEC1RST | OTFDEC1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the OTFDEC1. |
| OTFDEC2RST | OTFDEC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the OTFDEC2. |
| SDMMC1RST | SDMMC1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the SDMMC1. |
| SDMMC2RST | SDMMC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the SDMMC2. |