SYSCFGEN=B_0x0, SPI3EN=B_0x0, RTCAPBEN=B_0x0, COMPEN=B_0x0, OPAMPEN=B_0x0, I2C3EN=B_0x0, VREFEN=B_0x0, LPTIM3EN=B_0x0, LPTIM1EN=B_0x0, LPTIM4EN=B_0x0, LPUART1EN=B_0x0
RCC APB3 peripheral clock enable register
| SYSCFGEN | SYSCFG clock enable This bit is set and cleared by software. 0 (B_0x0): SYSCFG clock disabled 1 (B_0x1): SYSCFG clock enabled |
| SPI3EN | SPI3 clock enable This bit is set and cleared by software. 0 (B_0x0): SPI3 clock disabled 1 (B_0x1): SPI3 clock enabled |
| LPUART1EN | LPUART1 clock enable This bit is set and cleared by software. 0 (B_0x0): LPUART1 clock disabled 1 (B_0x1): LPUART1 clock enabled |
| I2C3EN | I2C3 clock enable This bit is set and cleared by software. 0 (B_0x0): I2C3 clock disabled 1 (B_0x1): I2C3 clock enabled |
| LPTIM1EN | LPTIM1 clock enable This bit is set and cleared by software. 0 (B_0x0): LPTIM1 clock disabled 1 (B_0x1): LPTIM1 clock enabled |
| LPTIM3EN | LPTIM3 clock enable This bit is set and cleared by software. 0 (B_0x0): LPTIM3 clock disabled 1 (B_0x1): LPTIM3 clock enabled |
| LPTIM4EN | LPTIM4 clock enable This bit is set and cleared by software. 0 (B_0x0): LPTIM4 clock disabled 1 (B_0x1): LPTIM4 clock enabled |
| OPAMPEN | OPAMP clock enable This bit is set and cleared by software. 0 (B_0x0): OPAMP clock disabled 1 (B_0x1): OPAMP clock enabled |
| COMPEN | COMP clock enable This bit is set and cleared by software. 0 (B_0x0): COMP clock disabled 1 (B_0x1): COMP clock enabled |
| VREFEN | VREFBUF clock enable This bit is set and cleared by software. 0 (B_0x0): VREFBUF clock disabled 1 (B_0x1): VREFBUF clock enabled |
| RTCAPBEN | RTC and TAMP APB clock enable This bit is set and cleared by software. 0 (B_0x0): RTC and TAMP APB clock disabled 1 (B_0x1): RTC and TAMP APB clock enabled |