SFTRSTF=B_0x0, LPWRRSTF=B_0x0, PINRSTF=B_0x0, RMVF=B_0x0, BORRSTF=B_0x0, IWDGRSTF=B_0x0, OBLRSTF=B_0x0, WWDGRSTF=B_0x0
RCC control/status register
| MSIKSRANGE | MSIK range after Standby mode This bit is set by software to chose the MSIK frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIK frequency. 4 (B_0x4): range 4 around 4M�Hz (reset value) 5 (B_0x5): range 5 around 2�MHz 6 (B_0x6): range 6 around 1.33�MHz 7 (B_0x7): range 7 around 1�MHz 8 (B_0x8): range 8 around 3.072�MHz |
| MSISSRANGE | MSIS range after Standby mode This bitfield is set by software to chose the MSIS frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIS frequency. 4 (B_0x4): range 4 around 4M�Hz (reset value) 5 (B_0x5): range 5 around 2�MHz 6 (B_0x6): range 6 around 1.33�MHz 7 (B_0x7): range 7 around 1�MHz 8 (B_0x8): range 8 around 3.072�MHz |
| RMVF | Remove reset flag This bit is set by software to clear the reset flags. 0 (B_0x0): No effect 1 (B_0x1): Clear the reset flags. |
| OBLRSTF | Option-byte loader reset flag This bit is set by hardware when a reset from the option-byte loading occurs. It is cleared by�writing to the RMVF bit. 0 (B_0x0): No reset from option-byte loading occurred 1 (B_0x1): Reset from option-byte loading occurred |
| PINRSTF | NRST pin reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to�the RMVF bit. 0 (B_0x0): No reset from NRST pin occurred 1 (B_0x1): Reset from NRST pin occurred |
| BORRSTF | Brownout reset or an exit from Shutdown mode reset flag This bit is set by hardware when a brownout reset or an exit from Shutdown mode reset occurs. It is cleared by writing to the RMVF bit. 0 (B_0x0): No BOR/exit from Shutdown mode reset occurred 1 (B_0x1): BOR/exit from Shutdown mode reset occurred |
| SFTRSTF | Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writing to RMVF. 0 (B_0x0): No software reset occurred 1 (B_0x1): Software reset occurred |
| IWDGRSTF | Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset domain occurs. It is cleared by writing to the RMVF bit. 0 (B_0x0): No independent watchdog reset occurred 1 (B_0x1): Independent watchdog reset occurred |
| WWDGRSTF | Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing to�the RMVF bit. 0 (B_0x0): No window watchdog reset occurred 1 (B_0x1): Window watchdog reset occurred |
| LPWRRSTF | Low-power reset flag This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shutdown mode entry, whereas the corresponding NRST_STOP, NRST_STBY, or NRST_SHDW option bit is cleared. This bit is cleared by writing to the RMVF bit. 0 (B_0x0): No illegal low-power mode reset occurred 1 (B_0x1): Illegal low-power mode reset occurred |