PLL1Q=B_0x0, PLL1R=B_0x0, PLL1P=B_0x0
RCC PLL1 dividers register
| PLL1N | Multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). … … Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded in PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16�MHz 3 (B_0x003): PLL1N = 4 4 (B_0x004): PLL1N = 5 5 (B_0x005): PLL1N = 6 128 (B_0x080): PLL1N = 129 (default after reset) 511 (B_0x1FF): PLL1N = 512 |
| PLL1P | PLL1 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll1_p_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). … 0 (B_0x0): Not allowed 1 (B_0x1): pll1_p_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_p_ck = vco1_ck 3 (B_0x3): pll1_p_ck = vco1_ck / 4 127 (B_0x7F): pll1_p_ck = vco1_ck / 128 |
| PLL1Q | PLL1 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll1_q_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). … 0 (B_0x0): pll1_q_ck = vco1_ck 1 (B_0x1): pll1_q_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_q_ck = vco1_ck / 3 3 (B_0x3): pll1_q_ck = vco1_ck / 4 127 (B_0x7F): pll1_q_ck = vco1_ck / 128 |
| PLL1R | PLL1 DIVR division factor This bitfield is set and reset by software to control frequency of the pll1_r_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Only division by one and even division factors are allowed. … 0 (B_0x0): Not allowed 1 (B_0x1): pll1_r_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_r_ck = vco1_ck / 3 3 (B_0x3): pll1_r_ck = vco1_ck / 4 127 (B_0x7F): pll1_r_ck = vco1_ck / 128 |