This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
| PCSTS | PCSTS |
| PCDET | PCDET |
| PENA | PENA |
| PENCHNG | PENCHNG |
| POCA | POCA |
| POCCHNG | POCCHNG |
| PRES | PRES |
| PSUSP | PSUSP |
| PRST | PRST |
| PLSTS | PLSTS |
| PPWR | PPWR |
| PTCTL | PTCTL |
| PSPD | PSPD |