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STMicroelectronics /STM32U575 /SDMMC1 /CMDR

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Interpret as CMDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CMDINDEX0 (CMDTRANS)CMDTRANS 0 (CMDSTOP)CMDSTOP 0WAITRESP 0 (WAITINT)WAITINT 0 (WAITPEND)WAITPEND 0 (CPSMEN)CPSMEN 0 (DTHOLD)DTHOLD 0 (BOOTMODE)BOOTMODE 0 (BOOTEN)BOOTEN 0 (CMDSUSPEND)CMDSUSPEND

Description

command register

Fields

CMDINDEX

Command index
CMDTRANS

The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM
CMDSTOP

The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
WAITRESP

Wait for response bits
WAITINT

CPSM waits for interrupt request
WAITPEND

CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM
CPSMEN

Command path state machine (CPSM) Enable bit
DTHOLD

Hold new data block transmission and reception in the DPSM
BOOTMODE

Select the boot mode procedure to be used
BOOTEN

Enable boot mode procedure
CMDSUSPEND

The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data