OSR=B_0x0, TROVS=B_0x0, ROVSE=B_0x0, LSHIFT=B_0x0, ROVSM=B_0x0, JOVSE=B_0x0, LFTRIG=B_0x0, OVSS=B_0x0, SMPTRIG=B_0x0, SWTRIG=B_0x0, BULB=B_0x0
ADC configuration register 2
| ROVSE | Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 0 (B_0x0): Regular Oversampling disabled 1 (B_0x1): Regular Oversampling enabled |
| JOVSE | Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing) 0 (B_0x0): Injected oversampling disabled 1 (B_0x1): Injected oversampling enabled |
| OVSS | Oversampling right shift This bit field is set and cleared by software to define the right shifting applied to the raw oversampling result. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): No right shift 1 (B_0x1): 1-bit right shift 2 (B_0x2): 2-bit right shift 3 (B_0x3): 3-bit right shift 4 (B_0x4): 4-bit right shift 5 (B_0x5): 5-bit right shift 6 (B_0x6): 6-bit right shift 7 (B_0x7): 7-bit right shift 8 (B_0x8): 8-bit right shift 9 (B_0x9): 9-bit right shift 10 (B_0xA): 10-bit right shift 11 (B_0xB): 11-bit right shift |
| TROVS | Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): All oversampled conversions for a channel are done consecutively following a trigger 1 (B_0x1): Each oversampled conversion for a channel needs a new trigger |
| ROVSM | Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 1 (B_0x1): Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start) |
| BULB | Bulb sampling mode This bit is set and cleared by software to select the bulb sampling mode. SMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Bulb sampling mode disabled 1 (B_0x1): Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion. |
| SWTRIG | Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Software trigger starts the conversion for sampling time control trigger mode 1 (B_0x1): Software trigger starts the sampling for sampling time control trigger mode. |
| SMPTRIG | Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN[1:0] bits must be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN[1:0] bits is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Sampling time control trigger mode disabled 1 (B_0x1): Sampling time control trigger mode enabled |
| OSR | Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2: 3x … 1023: 1024x Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1x (no oversampling) 1 (B_0x1): 2x |
| LFTRIG | Low-frequency trigger This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Low-frequency trigger mode disabled 1 (B_0x1): Low-frequency trigger mode enabled |
| LSHIFT | Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): No left shift 1 (B_0x1): 1-bit left shift 2 (B_0x2): 2-bit left shift 3 (B_0x3): 3-bit left shift 4 (B_0x4): 4-bit left shift 5 (B_0x5): 5-bit left shift 6 (B_0x6): 6-bit left shift 7 (B_0x7): 7-bit left shift 8 (B_0x8): 8-bit left shift 9 (B_0x9): 9-bit left shift 10 (B_0xA): 10-bit left shift 11 (B_0xB): 11-bit left shift 12 (B_0xC): 12-bit left shift 13 (B_0xD): 13-bit left shift 14 (B_0xE): 14-bit left shift 15 (B_0xF): 15-bit left shift |