AWD2IE=B_0x0, EOSMPIE=B_0x0, AWD3IE=B_0x0, EOCIE=B_0x0, EOSIE=B_0x0, AWD1IE=B_0x0, JEOCIE=B_0x0, OVRIE=B_0x0, JEOSIE=B_0x0, ADRDYIE=B_0x0
ADC interrupt enable register
| ADRDYIE | ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADRDY interrupt disabled 1 (B_0x1): ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. |
| EOSMPIE | End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 (B_0x0): EOSMP interrupt disabled. 1 (B_0x1): EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. |
| EOCIE | End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 (B_0x0): EOC interrupt disabled. 1 (B_0x1): EOC interrupt enabled. An interrupt is generated when the EOC bit is set. |
| EOSIE | End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 (B_0x0): EOS interrupt disabled 1 (B_0x1): EOS interrupt enabled. An interrupt is generated when the EOS bit is set. |
| OVRIE | Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 0 (B_0x0): Overrun interrupt disabled 1 (B_0x1): Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. |
| JEOCIE | End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: Software is allowed to write this bit only when JADSTART = 0 (which ensures that no regular conversion is ongoing). 0 (B_0x0): JEOC interrupt disabled. 1 (B_0x1): JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. |
| JEOSIE | End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: Software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). 0 (B_0x0): JEOS interrupt disabled 1 (B_0x1): JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set. |
| AWD1IE | Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog 1 interrupt disabled 1 (B_0x1): Analog watchdog 1 interrupt enabled |
| AWD2IE | Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog 2 interrupt disabled 1 (B_0x1): Analog watchdog 2 interrupt enabled |
| AWD3IE | Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog 3 interrupt disabled 1 (B_0x1): Analog watchdog 3 interrupt enabled |