OVR=B_0x0, ADRDY=B_0x0, EOS=B_0x0, AWD2=B_0x0, JEOC=B_0x0, JEOS=B_0x0, AWD3=B_0x0, EOC=B_0x0, LDORDY=B_0x0, AWD1=B_0x0, EOSMP=B_0x0
ADC interrupt and status register
| ADRDY | ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0 (B_0x0): ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): ADC is ready to start conversion |
| EOSMP | End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. 0 (B_0x0): not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): End of sampling phase reached |
| EOC | End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register 0 (B_0x0): Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Regular channel conversion complete |
| EOS | End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. 0 (B_0x0): Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Regular Conversions sequence complete |
| OVR | ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. 0 (B_0x0): No overrun occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Overrun has occurred |
| JEOC | Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register 0 (B_0x0): Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Injected channel conversion complete |
| JEOS | Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. 0 (B_0x0): Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Injected conversions complete |
| AWD1 | Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_LTR1, & ADC_HTR1 register. It is cleared by software. writing 1 to it. 0 (B_0x0): No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Analog watchdog 1 event occurred |
| AWD2 | Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_LTR2 & ADC_HTR2 register. It is cleared by software writing 1 to it. 0 (B_0x0): No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Analog watchdog 2 event occurred |
| AWD3 | Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_LTR3 & ADC_HTR3 register. It is cleared by software writing 1 to it. 0 (B_0x0): No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software) 1 (B_0x1): Analog watchdog 3 event occurred |
| LDORDY | ADC voltage regulator ready This bit is set by hardware. It indicates that the ADC internal supply is ready. The ADC is available after tADCVREG_SETUP time. 0 (B_0x0): ADC voltage regulator disabled 1 (B_0x1): ADC voltage regulator enabled |