STMicroelectronics /STM32U585 /FLASH /FLASH_NSCR

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Interpret as FLASH_NSCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PG 0 (B_0x0)PER 0 (MER1)MER1 0PNB0 (B_0x0)BKER 0 (BWR)BWR 0 (MER2)MER2 0 (STRT)STRT 0 (OPTSTRT)OPTSTRT 0 (B_0x0)EOPIE 0 (B_0x0)ERRIE 0 (B_0x0)OBL_LAUNCH 0 (OPTLOCK)OPTLOCK 0 (LOCK)LOCK

OBL_LAUNCH=B_0x0, ERRIE=B_0x0, BKER=B_0x0, PER=B_0x0, PG=B_0x0, EOPIE=B_0x0

Description

FLASH non-secure control register

Fields

PG

Non-secure programming

0 (B_0x0): Non-secure Flash programming disabled

1 (B_0x1): Non-secure Flash programming enabled

PER

Non-secure page erase

0 (B_0x0): Non-secure page erase disabled

1 (B_0x1): Non-secure page erase enabled

MER1

Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set.

PNB

Non-secure page number selection These bits select the page to erase. …

BKER

Non-secure bank selection for page erase

0 (B_0x0): Bank 1 selected for non-secure page erase

1 (B_0x1): Bank 2 selected for non-secure page erase

BWR

Non-secure burst write programming mode When set, this bit selects the burst write programming mode.

MER2

Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set.

STRT

Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR.

OPTSTRT

Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR.

EOPIE

Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1.

0 (B_0x0): Non-secure EOP Interrupt disabled

1 (B_0x1): Non-secure EOP Interrupt enabled

ERRIE

Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1.

0 (B_0x0): Non-secure OPERR error interrupt disabled

1 (B_0x1): Non-secure OPERR error interrupt enabled

OBL_LAUNCH

Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set.

0 (B_0x0): Option byte loading complete

1 (B_0x1): Option byte loading requested

OPTLOCK

Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset.

LOCK

Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.

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