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STMicroelectronics /STM32U585 /FMC /PCSCNTR

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Interpret as PCSCNTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CSCOUNT0 (CNTB1EN)CNTB1EN 0 (CNTB2EN)CNTB2EN 0 (CNTB3EN)CNTB3EN 0 (CNTB4EN)CNTB4EN

Description

PSRAM chip select counter register

Fields

CSCOUNT

Chip select counter
CNTB1EN

Counter Bank 1 enable
CNTB2EN

Counter Bank 2 enable
CNTB3EN

Counter Bank 3 enable
CNTB4EN

Counter Bank 4 enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data