LSM=B_0x0, PRIO=B_0x0, SUSPIE=B_0x0, USEIE=B_0x0, DTEIE=B_0x0, HTIE=B_0x0, RESET=B_0x0, EN=B_0x0, LAP=B_0x0, SUSP=B_0x0, TOIE=B_0x0, TCIE=B_0x0, ULEIE=B_0x0
GPDMA channel 2 control register
| EN | enable Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 (B_0x0): write: ignored, read: channel disabled 1 (B_0x1): write: enable channel, read: channel enabled |
| RESET | reset This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following:
0 (B_0x0): no channel reset 1 (B_0x1): channel reset |
| SUSP | suspend Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in . 0 (B_0x0): write: resume channel, read: channel not suspended 1 (B_0x1): write: suspend channel, read: channel suspended. |
| TCIE | transfer complete interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| HTIE | half transfer complete interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| DTEIE | data transfer error interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| ULEIE | update link transfer error interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| USEIE | user setting error interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| SUSPIE | completed suspension interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| TOIE | trigger overrun interrupt enable 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| LSM | Link step mode First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxBR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 0 (B_0x0): channel executed for the full linked-list and completed at the end of the last LLI (GPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxBR1.BRC[10:0] = 0 if present. 1 (B_0x1): channel executed once for the current LLI |
| LAP | linked-list allocated port This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1. 0 (B_0x0): port 0 (AHB) allocated 1 (B_0x1): port 1 (AHB) allocated |
| PRIO | priority level of the channel x GPDMA transfer versus others Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 0 (B_0x0): low priority, low weight 1 (B_0x1): low priority, mid weight 2 (B_0x2): low priority, high weight 3 (B_0x3): high priority |