DBX=B_0x0, DINC=B_0x0, DDW_LOG2=B_0x0, SSEC=B_0x0, SAP=B_0x0, DHX=B_0x0, SBX=B_0x0, DSEC=B_0x0, SDW_LOG2=B_0x0, DAP=B_0x0, PAM=B_0x0, SINC=B_0x0
GPDMA channel 5 transfer register 1
| SDW_LOG2 | binary logarithm of the source data width of a burst in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (GPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address GPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 (B_0x0): byte 1 (B_0x1): half-word (2 bytes) 2 (B_0x2): word (4 bytes) 3 (B_0x3): user setting error reported and no transfer issued |
| SINC | source incrementing burst The source address, pointed by GPDMA_CxSAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 0 (B_0x0): fixed burst 1 (B_0x1): contiguously incremented burst |
| SBL_1 | source burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If SBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width SDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. |
| PAM | padding/alignment mode If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else:
0 (B_0x0): source data is transferred as right aligned, padded with 0s up to the destination data width 0 (B_0x0): source data is transferred as right aligned, left-truncated down to the destination data width 1 (B_0x1): source data is transferred as right aligned, sign extended up to the destination data width 1 (B_0x1): source data is transferred as left-aligned, right-truncated down to the destination data width |
| SBX | source byte exchange within the unaligned half-word of each source word If the source data width is shorter than a word, this bit is ignored. If the source data width is a word: 0 (B_0x0): no byte-based exchange within the unaligned half-word of each source word 1 (B_0x1): the two consecutive bytes within the unaligned half-word of each source word are exchanged. |
| SAP | source allocated port This bit is used to allocate the master port for the source transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 0 (B_0x0): port 0 (AHB) allocated 1 (B_0x1): port 1 (AHB) allocated |
| SSEC | security attribute of the GPDMA transfer from the source If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx =1 . A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure. 0 (B_0x0): GPDMA transfer non-secure 1 (B_0x1): GPDMA transfer secure |
| DDW_LOG2 | binary logarithm of the destination data width of a burst, in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0], versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is issued. 0 (B_0x0): byte 1 (B_0x1): half-word (2 bytes) 2 (B_0x2): word (4 bytes) 3 (B_0x3): user setting error reported and no transfer issued |
| DINC | destination incrementing burst The destination address, pointed by GPDMA_CxDAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 0 (B_0x0): fixed burst 1 (B_0x1): contiguously incremented burst |
| DBL_1 | destination burst length minus 1, between 0 and 63 The burst length unit is one data named beat within a burst. If DBL_1[5:0] =0 , the burst can be named as single. Each data/beat has a width defined by the destination data width DDW_LOG2[1:0]. Note: If a burst transfer crossed a 1-Kbyte address boundary on a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the AHB protocol. If a burst transfer is of length greater than the FIFO size of the channel x, the GPDMA modifies and shortens the programmed burst into singles or bursts of lower length, to be compliant with the FIFO size. Transfer performance is lower, with GPDMA re-arbitration between effective and lower bursts/singles, but the data integrity is guaranteed. |
| DBX | destination byte exchange If the destination data size is a byte, this bit is ignored. If the destination data size is not a byte: 0 (B_0x0): no byte-based exchange within half-word 1 (B_0x1): the two consecutive (post PAM) bytes are exchanged in each destination half-word. |
| DHX | destination half-word exchange If the destination data size is shorter than a word, this bit is ignored. If the destination data size is a word: 0 (B_0x0): no halfword-based exchanged within word 1 (B_0x1): the two consecutive (post PAM) half-words are exchanged in each destination word. |
| DAP | destination allocated port This bit is used to allocate the master port for the destination transfer Note: This bit must be written when EN = 0. This bit is read-only when EN = 1. 0 (B_0x0): port 0 (AHB) allocated 1 (B_0x1): port 1 (AHB) allocated |
| DSEC | security attribute of the GPDMA transfer to the destination If GPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx = 1. A secure write is ignored when GPDMA_SECCFGR.SECx = 0. When GPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure. 0 (B_0x0): GPDMA transfer non-secure 1 (B_0x1): GPDMA transfer secure |