ULL=B_0x0, UT2=B_0x0, USA=B_0x0, UDA=B_0x0, UT1=B_0x0, UB1=B_0x0
GPDMA channel 9 linked-list address register
| LA | pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list GPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list GPDMA internal register file (GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. |
| ULL | Update GPDMA_CxLLR register from memory This bit is used to control the update of GPDMA_CxLLR from the memory during the link transfer. 0 (B_0x0): no GPDMA_CxLLR update 1 (B_0x1): GPDMA_CxLLR update |
| UDA | Update GPDMA_CxDAR register from memory This bit is used to control the update of GPDMA_CxDAR from the memory during the link transfer. 0 (B_0x0): no GPDMA_CxDAR update 1 (B_0x1): GPDMA_CxDAR update |
| USA | update GPDMA_CxSAR from memory This bit controls the update of GPDMA_CxSAR from the memory during the link transfer. 0 (B_0x0): no GPDMA_CxSAR update 1 (B_0x1): GPDMA_CxSAR update |
| UB1 | Update GPDMA_CxBR1 from memory This bit controls the update of GPDMA_CxBR1 from the memory during the link transfer. If UB1 = 0 and if GPDMA_CxLLR ≠ 0, the linked-list is not completed. GPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. 0 (B_0x0): no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer) 1 (B_0x1): GPDMA_CxBR1 update |
| UT2 | Update GPDMA_CxTR2 from memory This bit controls the update of GPDMA_CxTR2 from the memory during the link transfer. 0 (B_0x0): no GPDMA_CxTR2 update 1 (B_0x1): GPDMA_CxTR2 update |
| UT1 | Update GPDMA_CxTR1 from memory This bit controls the update of GPDMA_CxTR1 from the memory during the link transfer. 0 (B_0x0): no GPDMA_CxTR1 update 1 (B_0x1): GPDMA_CxTR1 update |