SSEC=B_0x0, DDW_LOG2=B_0x0, PAM=B_0x0, DSEC=B_0x0, DINC=B_0x0, SINC=B_0x0, SDW_LOG2=B_0x0
LPDMA channel 2 transfer register 1
| SDW_LOG2 | binary logarithm of the source data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. a source block size must be a multiple of the source data width (LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued. 0 (B_0x0): byte 1 (B_0x1): half-word (2 bytes) 2 (B_0x2): word (4 bytes) 3 (B_0x3): user setting error reported and no transfer issued |
| SINC | source incrementing single The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer. 0 (B_0x0): fixed single 1 (B_0x1): contiguously incremented single |
| PAM | padding/alignment mode If DDW_LOG2[1:0]=SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored. Else: Case 1: If destination data width > source data width Case 2: If destination data width < source data width 0 (B_0x0): source data is transferred as right aligned, left-truncated down to the destination data width 0 (B_0x0): source data is transferred as right aligned, padded with 0s up to the destination data width 1 (B_0x1): source data is transferred as left-aligned, right-truncated down to the destination data width 1 (B_0x1): source data is transferred as right aligned, sign extended up to the destination data width |
| SSEC | security attribute of the LPDMA transfer from the source If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx =1 . A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure. 0 (B_0x0): LPDMA transfer non-secure 1 (B_0x1): LPDMA transfer secure |
| DDW_LOG2 | binary logarithm of the destination data width of a single in bytes Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued. 0 (B_0x0): byte 1 (B_0x1): half-word (2 bytes) 2 (B_0x2): word (4 bytes) 3 (B_0x3): user setting error reported and no transfer issued |
| DINC | destination incrementing single The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer. 0 (B_0x0): fixed single 1 (B_0x1): contiguously incremented single |
| DSEC | security attribute of the LPDMA transfer to the destination If LPDMA_SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0. When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure. 0 (B_0x0): LPDMA transfer non-secure 1 (B_0x1): LPDMA transfer secure |