UT1=B_0x0, UT2=B_0x0, ULL=B_0x0, UB1=B_0x0, UDA=B_0x0, USA=B_0x0
LPDMA channel 3 linked-list address register
| LA | pointer (16-bit low-significant address) to the next linked-list data structure If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored. |
| ULL | Update LPDMA_CxLLR register from memory This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer. 0 (B_0x0): no LPDMA_CxLLR update 1 (B_0x1): LPDMA_CxLLR update |
| UDA | Update LPDMA_CxDAR register from memory This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer. 0 (B_0x0): no LPDMA_CxDAR update 1 (B_0x1): LPDMA_CxDAR update |
| USA | update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. 0 (B_0x0): no LPDMA_CxSAR update 1 (B_0x1): LPDMA_CxSAR update |
| UB1 | Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. 0 (B_0x0): no LPDMA_CxBR1 update from memory and internally restored to the previous programmed value 1 (B_0x1): LPDMA_CxBR1 update |
| UT2 | Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. 0 (B_0x0): no LPDMA_CxTR2 update 1 (B_0x1): LPDMA_CxTR2 update |
| UT1 | Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. 0 (B_0x0): no LPDMA_CxTR1 update 1 (B_0x1): LPDMA_CxTR1 update |