CRSSMEN=B_0x0, TIM4SMEN=B_0x0, TIM7SMEN=B_0x0, I2C1SMEN=B_0x0, I2C2SMEN=B_0x0, USART3SMEN=B_0x0, USART2SMEN=B_0x0, UART5SMEN=B_0x0, SPI2SMEN=B_0x0, TIM3SMEN=B_0x0, USART6SMEN=B_0x0, TIM6SMEN=B_0x0, WWDGSMEN=B_0x0, TIM5SMEN=B_0x0, UART4SMEN=B_0x0, TIM2SMEN=B_0x0
RCC APB1 peripheral clock enable in Sleep and Stop modes register 1
| TIM2SMEN | TIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM2 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM3SMEN | TIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM3 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM3 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM4SMEN | TIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM4 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM4 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM5SMEN | TIM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM5 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM5 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM6SMEN | TIM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM6 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM6 clocks enabled by the clock gating during Sleep and Stop modes |
| TIM7SMEN | TIM7 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TIM7 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM7 clocks enabled by the clock gating during Sleep and Stop modes |
| WWDGSMEN | Window watchdog clock enable during Sleep and Stop modes This bit is set and cleared by software. It is forced to one by hardware when the hardware WWDG option is activated. 0 (B_0x0): Window watchdog clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): Window watchdog clocks enabled by the clock gating during Sleep and Stop modes |
| SPI2SMEN | SPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): SPI2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SPI2 clocks enabled by the clock gating during Sleep and Stop modes |
| USART2SMEN | USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): USART2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): USART2 clocks enabled by the clock gating during Sleep and Stop modes |
| USART3SMEN | USART3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): USART3 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): USART3 clocks enabled by the clock gating during Sleep and Stop modes |
| UART4SMEN | UART4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): UART4 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): UART4 clocks enabled by the clock gating during Sleep and Stop modes |
| UART5SMEN | UART5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): UART5 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): UART5 clocks enabled by the clock gating during Sleep and Stop modes |
| I2C1SMEN | I2C1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): I2C1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C1 clocks enabled by the clock gating during Sleep and Stop modes |
| I2C2SMEN | I2C2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): I2C2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C2 clocks enabled by the clock gating during Sleep and Stop modes |
| CRSSMEN | CRS clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): CRS clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): CRS clocks enabled by the clock gating during Sleep and Stop modes |
| USART6SMEN | USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): USART6 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): USART6 clocks enabled by the clock gating during Sleep and Stop modes |