AHB3DIS=B_0x0, APB3DIS=B_0x0
RCC clock configuration register 3
| PPRE3 | APB3 prescaler This bitfield is set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided 4 (B_0x4): HCLK divided by 2 5 (B_0x5): HCLK divided by 4 6 (B_0x6): HCLK divided by 8 7 (B_0x7): HCLK divided by 16 |
| AHB3DIS | AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4. 0 (B_0x0): AHB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): AHB3 clock disabled |
| APB3DIS | APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. 0 (B_0x0): APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): APB3 clock disabled |