MSSI=B_0x0, COMM=B_0x0, SP=B_0x0, RDIOM=B_0x0, RDIOP=B_0x0, AFCNTR=B_0x0, LSBFRST=B_0x0, MIDI=B_0x0, MASTER=B_0x0, IOSWP=B_0x0, SSOM=B_0x0, SSIOP=B_0x0, SSOE=B_0x0, CPOL=B_0x0, CPHA=B_0x0, SSM=B_0x0
SPI configuration register 2
| MSSI | Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS opening a session and the beginning of the first data frame of the session in Master mode when SSOE is enabled. … Note: This feature is not supported in TI mode. To include the delay, the SPI must be disabled and re-enabled between sessions. 0 (B_0x0): no extra delay 1 (B_0x1): 1 clock cycle period delay added 15 (B_0xF): 15 clock cycle periods delay added |
| MIDI | master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in Master mode. … Note: This feature is not supported in TI mode. 0 (B_0x0): no delay 1 (B_0x1): 1 clock cycle period delay 15 (B_0xF): 15 clock cycle periods delay |
| RDIOM | RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero. 0 (B_0x0): RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect) 1 (B_0x1): RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) |
| RDIOP | RDY signal input/output polarity 0 (B_0x0): high level of the signal means the slave is ready for communication 1 (B_0x1): low level of the signal means the slave is ready for communication |
| IOSWP | swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. Original MISO pin becomes MOSI and original MOSI pin becomes MISO. 0 (B_0x0): no swap 1 (B_0x1): MOSI and MISO are swapped |
| COMM | SPI Communication Mode 0 (B_0x0): full-duplex 1 (B_0x1): simplex transmitter 2 (B_0x2): simplex receiver 3 (B_0x3): half-duplex |
| SP | serial protocol others: reserved, must not be used 0 (B_0x0): SPI Motorola 1 (B_0x1): SPI TI |
| MASTER | SPI Master 0 (B_0x0): SPI Slave 1 (B_0x1): SPI Master |
| LSBFRST | data frame format 0 (B_0x0): MSB transmitted first 1 (B_0x1): LSB transmitted first |
| CPHA | clock phase 0 (B_0x0): the first clock transition is the first data capture edge 1 (B_0x1): the second clock transition is the first data capture edge |
| CPOL | clock polarity 0 (B_0x0): SCK signal is at 0 when idle 1 (B_0x1): SCK signal is at 1 when idle |
| SSM | software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the SS signal input is forced to not active state internally to prevent master mode fault error. 0 (B_0x0): SS input value is determined by the SS PAD 1 (B_0x1): SS input value is determined by the SSI bit |
| SSIOP | SS input/output polarity 0 (B_0x0): low level is active for SS signal 1 (B_0x1): high level is active for SS signal |
| SSOE | SS output enable This bit is taken into account in Master mode only 0 (B_0x0): SS output is disabled and the SPI can work in multi-master configuration 1 (B_0x1): SS output is enabled. The SPI cannot work in a multi-master environment. It forces the SS pin at inactive level after the transfer is completed or SPI is disabled with respect to SSOM, MIDI, MSSI, SSIOP bits setting |
| SSOM | SS output management in Master mode This bit is taken into account in Master mode when SSOE is enabled. It allows the SS output to be configured between two consecutive data transfers. 0 (B_0x0): SS is kept at active level till data transfer is completed, it becomes inactive with EOT flag 1 (B_0x1): SPI data frames are interleaved with SS non active pulses when MIDI[3:0]>1 |
| AFCNTR | alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be disabled temporary for a specific configuration reason (e.g. CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. 0 (B_0x0): The peripheral takes no control of GPIOs while it is disabled 1 (B_0x1): The peripheral keeps always control of all associated GPIOs |