IOLOCK=B_0x0, CRC33_17=B_0x0, CSTART=B_0x0, MASRX=B_0x0, SPE=B_0x0, HDDIR=B_0x0, RCRCINI=B_0x0, TCRCINI=B_0x0
| SPE | serial peripheral enable This bit is set by and cleared by software. When SPE=1, SPI data transfer is enabled, SPI_CFG1 and SPI_CFG2 configuration registers, CRCPOLY, UDRDR, part of SPI_AUTOCR register and IOLOCK bit in the SPI_CR1 register are write protected. They can be changed only when SPE=0. When SPE=0 any SPI operation is stopped and disabled, all the pending requests of the events with enabled interrupt are blocked except the MODF interrupt request (but their pending still propagates the request of the spi_plck clock), the SS output is deactivated at master, the RDY signal keeps not ready status at slave, the internal state machine is reseted, all the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero. SPE is cleared and cannot be set when MODF error flag is active. 0 (B_0x0): Serial peripheral disabled. 1 (B_0x1): Serial peripheral enabled |
| MASRX | master automatic suspension in Receive mode This bit is set and cleared by software to control continuous SPI transfer in master receiver mode and automatic management in order to avoid overrun condition. When SPI communication is suspended by hardware automatically, it could happen that few bits of next frame are already clocked out due to internal synchronization delay. This is why, the automatic suspension is not quite reliable when size of data drops below 8 bits. In this case, a safe suspension can be achieved by combination with delay inserted between data frames applied when MIDI parameter keeps a non zero value; sum of data size and the interleaved SPI cycles should always produce interval at length of 8 SPI clock periods at minimum. After software clearing of the SUSP bit, the communication resumes and continues by subsequent bits transaction without any next constraint. Prior the SUSP bit is cleared, the user must release the RxFIFO space as much as possible by reading out all the data packets available at RxFIFO based on the RXP flag indication to prevent any subsequent suspension. 0 (B_0x0): SPI flow/clock generation is continuous, regardless of overrun condition. (data are lost) 1 (B_0x1): SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. The SUSP flag is set when the SPI communication is suspended. |
| CSTART | master transfer start This bit can be set by software if SPI is enabled only to start an SPI communication. it is cleared by hardware when end of transfer (EOT) flag is set or when a transaction suspend request is accepted. In SPI mode, the bit is taken into account at master mode only. If transmission is enabled, communication starts or continues only if any data is available in the transmission FIFO. 0 (B_0x0): master transfer is at idle 1 (B_0x1): master transfer is on-going or temporary suspended by automatic suspend |
| CSUSP | master SUSPend request This bit reads as zero. In Master mode, when this bit is set by software, the CSTART bit is reset at the end of the current frame and SPI communication is suspended. The user has to check SUSP flag to check end of the frame transaction. The Master mode communication must be suspended (using this bit or keeping TXDR empty) before disabling the SPI or going to Low-power mode. After software suspension, SUSP flag has to be cleared and SPI disabled and re-enabled before the next transaction starts. |
| HDDIR | Rx/Tx direction at Half-duplex mode In Half-Duplex configuration the HDDIR bit establishes the Rx/Tx direction of the data transfer. This bit is ignored in Full-Duplex or any Simplex configuration. 0 (B_0x0): SPI is Receiver 1 (B_0x1): SPI is transmitter |
| SSI | internal SS signal input level This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the peripheral SS input internally and the I/O value of the SS pin is ignored. |
| CRC33_17 | 32-bit CRC polynomial configuration 0 (B_0x0): Full size (33-bit or 17-bit) CRC polynomial is not used 1 (B_0x1): Full size (33-bit or 17-bit) CRC polynomial is used |
| RCRCINI | CRC calculation initialization pattern control for receiver 0 (B_0x0): All zero pattern is applied 1 (B_0x1): All ones pattern is applied |
| TCRCINI | CRC calculation initialization pattern control for transmitter 0 (B_0x0): all zero pattern is applied 1 (B_0x1): all ones pattern is applied |
| IOLOCK | locking the AF configuration of associated IOs This bit is set by software and cleared by hardware whenever the SPE bit is changed from 1 to 0. When this bit is set, SPI_CFG2 register content cannot be modified. This bit can be set when SPI is disabled only else it is write protected. It is cleared and cannot be set when MODF bit is set. 0 (B_0x0): AF configuration is not locked 1 (B_0x1): AF configuration is locked |