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STMicroelectronics /STM32U585 /TIM1 /TIM1_AF2

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Interpret as TIM1_AF2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BK2INE 0 (B_0x0)BK2CMP1E 0 (B_0x0)BK2CMP2E 0 (B_0x0)BK2CMP3E 0 (B_0x0)BK2CMP4E 0 (B_0x0)BK2CMP5E 0 (B_0x0)BK2CMP6E 0 (B_0x0)BK2CMP7E 0 (B_0x0)BK2CMP8E 0 (B_0x0)BK2INP 0 (B_0x0)BK2CMP1P 0 (B_0x0)BK2CMP2P 0 (B_0x0)BK2CMP3P 0 (B_0x0)BK2CMP4P 0 (B_0x0)OCRSEL

BK2CMP4P=B_0x0, BK2CMP5E=B_0x0, BK2CMP4E=B_0x0, BK2CMP1P=B_0x0, BK2CMP2P=B_0x0, OCRSEL=B_0x0, BK2INP=B_0x0, BK2CMP8E=B_0x0, BK2CMP6E=B_0x0, BK2INE=B_0x0, BK2CMP1E=B_0x0, BK2CMP3P=B_0x0, BK2CMP3E=B_0x0, BK2CMP7E=B_0x0, BK2CMP2E=B_0x0

Description

TIM1 alternate function register 2

Fields

BK2INE

TIMx_BKIN2 input enable This bit enables the TIMx_BKIN2 alternate function input for the timer’s tim_brk2 input. TIMx_BKIN2 input is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): TIMx_BKIN2 input disabled

1 (B_0x1): TIMx_BKIN2 input enabled
BK2CMP1E

tim_brk2_cmp1 enable This bit enables the tim_brk2_cmp1 for the timer’s tim_brk2 input. tim_brk2_cmp1 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp1 input disabled

1 (B_0x1): tim_brk2_cmp1 input enabled
BK2CMP2E

tim_brk2_cmp2 enable This bit enables the tim_brk2_cmp2 for the timer’s tim_brk2 input. tim_brk2_cmp2 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp2 input disabled

1 (B_0x1): tim_brk2_cmp2 input enabled
BK2CMP3E

tim_brk2_cmp3 enable This bit enables the tim_brk2_cmp3 for the timer’s tim_brk2 input. tim_brk2_cmp3 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp3 input disabled

1 (B_0x1): tim_brk2_cmp3 input enabled
BK2CMP4E

tim_brk2_cmp4 enable This bit enables the tim_brk2_cmp4 for the timer’s tim_brk2 input. tim_brk2_cmp4 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp4 input disabled

1 (B_0x1): tim_brk2_cmp4 input enabled
BK2CMP5E

tim_brk2_cmp5 enable This bit enables the tim_brk2_cmp5 for the timer’s tim_brk2 input. tim_brk2_cmp5 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp5 input disabled

1 (B_0x1): tim_brk2_cmp5 input enabled
BK2CMP6E

tim_brk2_cmp6 enable This bit enables the tim_brk2_cmp6 for the timer’s tim_brk2 input. tim_brk2_cmp6 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp6 input disabled

1 (B_0x1): tim_brk2_cmp6 input enabled
BK2CMP7E

tim_brk2_cmp7 enable This bit enables the tim_brk2_cmp7 for the timer’s tim_brk2 input. tim_brk2_cmp7 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp7 input disabled

1 (B_0x1): tim_brk2_cmp7 input enabled
BK2CMP8E

tim_brk2_cmp8 enable This bit enables the tim_brk2_cmp8 for the timer’s tim_brk2 input. tim_brk2_cmp8 output is 'ORed’ with the other tim_brk2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp8 input disabled

1 (B_0x1): tim_brk2_cmp8 input enabled
BK2INP

TIMx_BKIN2 input polarity This bit selects the TIMx_BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): TIMx_BKIN2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)

1 (B_0x1): TIMx_BKIN2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)
BK2CMP1P

tim_brk2_cmp1 input polarity This bit selects the tim_brk2_cmp1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp1 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)

1 (B_0x1): tim_brk2_cmp1 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)
BK2CMP2P

tim_brk2_cmp2 input polarity This bit selects the tim_brk2_cmp2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp2 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)

1 (B_0x1): tim_brk2_cmp2 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)
BK2CMP3P

tim_brk2_cmp3 input polarity This bit selects the tim_brk2_cmp3 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp3 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)

1 (B_0x1): tim_brk2_cmp3 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)
BK2CMP4P

tim_brk2_cmp4 input polarity This bit selects the tim_brk2_cmp4 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_brk2_cmp4 input polarity is not inverted (active low if BK2P = 0, active high if BK2P = 1)

1 (B_0x1): tim_brk2_cmp4 input polarity is inverted (active high if BK2P = 0, active low if BK2P = 1)
OCRSEL

ocref_clr source selection These bits select the ocref_clr input source. … Refer to for product specific information. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): tim_ocref_clr0

1 (B_0x1): tim_ocref_clr1

7 (B_0x7): tim_ocref_clr7

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data