STMicroelectronics /STM32U585 /TIM1 /TIM1_CCER

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Interpret as TIM1_CCER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CC1E 0 (B_0x0)CC1P 0 (B_0x0)CC1NE 0 (B_0x0)CC1NP 0 (CC2E)CC2E 0 (CC2P)CC2P 0 (CC2NE)CC2NE 0 (CC2NP)CC2NP 0 (CC3E)CC3E 0 (CC3P)CC3P 0 (CC3NE)CC3NE 0 (CC3NP)CC3NP 0 (CC4E)CC4E 0 (CC4P)CC4P 0 (CC4NE)CC4NE 0 (CC4NP)CC4NP 0 (CC5E)CC5E 0 (CC5P)CC5P 0 (CC6E)CC6E 0 (CC6P)CC6P

CC1NP=B_0x0, CC1E=B_0x0, CC1P=B_0x0, CC1NE=B_0x0

Description

TIM1 capture/compare enable register

Fields

CC1E

Capture/compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated.

0 (B_0x0): Capture mode disabled / OC1 is not active (see below)

1 (B_0x1): Capture mode enabled / OC1 signal is output on the corresponding output pin

CC1P

Capture/compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: the configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.

0 (B_0x0): OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)

1 (B_0x1): OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)

CC1NE

Capture/compare 1 complementary output enable Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated.

0 (B_0x0): Off - tim_oc1n is not active. tim_oc1n level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

1 (B_0x1): On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

CC1NP

Capture/compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of tim_ti1fp1 and tim_ti2fp1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (channel configured as output). Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.

0 (B_0x0): tim_oc1n active high.

1 (B_0x1): tim_oc1n active low.

CC2E

Capture/compare 2 output enable Refer to CC1E description

CC2P

Capture/compare 2 output polarity Refer to CC1P description

CC2NE

Capture/compare 2 complementary output enable Refer to CC1NE description

CC2NP

Capture/compare 2 complementary output polarity Refer to CC1NP description

CC3E

Capture/compare 3 output enable Refer to CC1E description

CC3P

Capture/compare 3 output polarity Refer to CC1P description

CC3NE

Capture/compare 3 complementary output enable Refer to CC1NE description

CC3NP

Capture/compare 3 complementary output polarity Refer to CC1NP description

CC4E

Capture/compare 4 output enable Refer to CC1E description

CC4P

Capture/compare 4 output polarity Refer to CC1P description

CC4NE

Capture/compare 4 complementary output enable Refer to CC1NE description

CC4NP

Capture/compare 4 complementary output polarity Refer to CC1NP description

CC5E

Capture/compare 5 output enable Refer to CC1E description

CC5P

Capture/compare 5 output polarity Refer to CC1P description

CC6E

Capture/compare 6 output enable Refer to CC1E description

CC6P

Capture/compare 6 output polarity Refer to CC1P description

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