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STMicroelectronics /STM32U585 /TIM1 /TIM1_CCMR2_Input

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Interpret as TIM1_CCMR2_Input

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CC3S 0IC3PSC 0IC3F0 (B_0x0)CC4S 0IC4PSC 0IC4F

CC4S=B_0x0, CC3S=B_0x0

Description

TIM1 capture/compare mode register 2 [alternate]

Fields

CC3S

Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0’ in TIMx_CCER).

0 (B_0x0): CC3 channel is configured as output

1 (B_0x1): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3

2 (B_0x2): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4

3 (B_0x3): CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
IC3PSC

Input capture 3 prescaler
IC3F

Input capture 3 filter
CC4S

Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0’ in TIMx_CCER).

0 (B_0x0): CC4 channel is configured as output

1 (B_0x1): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4

2 (B_0x2): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3

3 (B_0x3): CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
IC4PSC

Input capture 4 prescaler
IC4F

Input capture 4 filter

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data