GC5C1=B_0x0, GC5C3=B_0x0, GC5C2=B_0x0
TIM1 capture/compare register 5
| CCR5 | Capture/compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on tim_oc5 output. Non-dithering mode (DITHEN = 0) The register holds the compare value in CCR5[15:0]. The CCR5[19:16] bits are reset. Dithering mode (DITHEN = 1) The register holds the integer part in CCR5[19:4]. The CCR5[3:0] bitfield contains the dithered part. |
| GC5C1 | Group channel 5 and channel 1 Distortion on channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 0 (B_0x0): No effect of oc5ref on oc1refc 1 (B_0x1): oc1refc is the logical AND of oc1ref and oc5ref |
| GC5C2 | Group channel 5 and channel 2 Distortion on channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 0 (B_0x0): No effect of tim_oc5ref on tim_oc2refc 1 (B_0x1): tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref |
| GC5C3 | Group channel 5 and channel 3 Distortion on channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 0 (B_0x0): No effect of tim_oc5ref on tim_oc3refc 1 (B_0x1): tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref |