IE=B_0x0, FIDX=B_0x0, IPOS=B_0x0, IBLK=B_0x0, IDIR=B_0x0
TIM1 timer encoder control register
| IE | Index enable This bit indicates if the Index event resets the counter. 0 (B_0x0): Index disabled 1 (B_0x1): Index enabled |
| IDIR | Index direction This bit indicates in which direction the Index event resets the counter. Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled). 0 (B_0x0): Index resets the counter whatever the direction 1 (B_0x1): Index resets the counter when up-counting only 2 (B_0x2): Index resets the counter when down-counting only |
| IBLK | Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input 0 (B_0x0): Index always active 1 (B_0x1): Index disabled hen tim_ti3 input is active, as per CC3P bitfield 2 (B_0x2): Index disabled when tim_ti4 input is active, as per CC4P bitfield |
| FIDX | First index This bit indicates if the first index only is taken into account 0 (B_0x0): Index is always active 1 (B_0x1): the first Index only resets the counter |
| IPOS | Index positioning In quadrature encoder mode (SMS[3:0] = 0001, 0010, 0011, 1110, 1111), this bit indicates in which AB input configuration the Index event resets the counter. In directional clock mode or clock plus direction mode (SMS[3:0] = 1010, 1011, 1100, 1101), these bits indicates on which level the Index event resets the counter. In bidirectional clock mode, this applies for both clock inputs. x0: Index resets the counter when clock is 0 x1: Index resets the counter when clock is 1 Note: IPOS[1]âbit is not significant 0 (B_0x0): Index resets the counter when AB = 00 1 (B_0x1): Index resets the counter when AB = 01 2 (B_0x2): Index resets the counter when AB = 10 3 (B_0x3): Index resets the counter when AB = 11 |
| PW | Pulse width This bitfield defines the pulse duration, as following: tPW = PW[7:0] x tPWG |
| PWPRSC | Pulse width prescaler This bitfield sets the clock prescaler for the pulse generator, as following: tPWG = (2(PWPRSC[2:0])) x ttim_ker_ck |