TIF=B_0x0, DIRF=B_0x0, COMIF=B_0x0, UIF=B_0x0, B2IF=B_0x0, BIF=B_0x0, CC1IF=B_0x0, IERRF=B_0x0, TERRF=B_0x0, SBIF=B_0x0, IDXF=B_0x0, CC1OF=B_0x0
TIM1 status register
| UIF | Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 0 (B_0x0): No update occurred. 1 (B_0x1): Update interrupt pending. This bit is set by hardware when the registers are updated: |
| CC1IF | Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in downcounting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 0 (B_0x0): No compare match / No input capture occurred 1 (B_0x1): A compare match or an input capture occurred |
| CC2IF | Capture/compare 2 interrupt flag Refer to CC1IF description |
| CC3IF | Capture/compare 3 interrupt flag Refer to CC1IF description |
| CC4IF | Capture/compare 4 interrupt flag Refer to CC1IF description |
| COMIF | COM interrupt flag This flag is set by hardware on COM event (when capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0 (B_0x0): No COM event occurred. 1 (B_0x1): COM interrupt pending. |
| TIF | Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on tim_trgi input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0 (B_0x0): No trigger event occurred. 1 (B_0x1): Trigger interrupt pending. |
| BIF | Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0 (B_0x0): No break event occurred. 1 (B_0x1): An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. |
| B2IF | Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0 (B_0x0): No break event occurred. 1 (B_0x1): An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register. |
| CC1OF | Capture/compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â. 0 (B_0x0): No overcapture has been detected. 1 (B_0x1): The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set |
| CC2OF | Capture/compare 2 overcapture flag Refer to CC1OF description |
| CC3OF | Capture/compare 3 overcapture flag Refer to CC1OF description |
| CC4OF | Capture/compare 4 overcapture flag Refer to CC1OF description |
| SBIF | System break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0 (B_0x0): No break event occurred. 1 (B_0x1): An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register. |
| CC5IF | Compare 5 interrupt flag Refer to CC1IF description Note: Channel 5 can only be configured as output. |
| CC6IF | Compare 6 interrupt flag Refer to CC1IF description Note: Channel 6 can only be configured as output. |
| IDXF | Index interrupt flag This flag is set by hardware when an index event is detected. It is cleared by software by writing it to '0â. 0 (B_0x0): No index event occurred. 1 (B_0x1): An index event has occurred |
| DIRF | Direction change interrupt flag This flag is set by hardware when the direction changes in encoder mode (DIR bit value in TIMx_CR is changing). It is cleared by software by writing it to '0â. 0 (B_0x0): No direction change 1 (B_0x1): Direction change |
| IERRF | Index error interrupt flag This flag is set by hardware when an index error is detected. It is cleared by software by writing it to '0â. 0 (B_0x0): No index error has been detected. 1 (B_0x1): An index error has been detected |
| TERRF | Transition error interrupt flag This flag is set by hardware when a transition error is detected in encoder mode. It is cleared by software by writing it to '0â. 0 (B_0x0): No encoder transition error has been detected. 1 (B_0x1): An encoder transition error has been detected |