RXDMAEN=B_0x0, HBITCLKDIV=B_0x0, TRANSWIN=B_0x0, IFRGAP=B_0x0, TXDMAEN=B_0x0, UCPDEN=B_0x0, PSC_USBPDCLK=B_0x0
UCPD configuration register 1
| HBITCLKDIV | Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a ucpd_clk divider producing half-bit clock (hbit_clk). 0 (B_0x0): 1 (bypass) 26 (B_0x1A): 27 63 (B_0x3F): 64 |
| IFRGAP | Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal. 0 (B_0x0): Not supported 1 (B_0x1): 2 13 (B_0xD): 14 14 (B_0xE): 15 15 (B_0xF): 16 31 (B_0x1F): 32 |
| TRANSWIN | Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting. 0 (B_0x0): Not supported 1 (B_0x1): 2 9 (B_0x9): 10 (recommended) 31 (B_0x1F): 32 |
| PSC_USBPDCLK | Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz. 0 (B_0x0): 1 (bypass) 1 (B_0x1): 2 2 (B_0x2): 4 3 (B_0x3): 8 4 (B_0x4): 16 |
| RXORDSETEN | Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP’ detect enabled 0bxxxxxx1xx: SOP’’ detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP’_Debug enabled 0bxx1xxxxxx: SOP’'_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled |
| TXDMAEN | Transmission DMA mode enable When set, the bit enables DMA mode for transmission. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| RXDMAEN | Reception DMA mode enable When set, the bit enables DMA mode for reception. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| UCPDEN | UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state. 0 (B_0x0): Disable 1 (B_0x1): Enable |