RXERR=B_0x0, TYPEC_VSTATE_CC1=B_0x0, RXORDDET=B_0x0, TXUND=B_0x0, TXMSGABT=B_0x0, RXMSGEND=B_0x0, TYPECEVT1=B_0x0, TXMSGSENT=B_0x0, RXOVR=B_0x0, RXHRSTDET=B_0x0, TYPEC_VSTATE_CC2=B_0x0, RXNE=B_0x0, TYPECEVT2=B_0x0, FRSEVT=B_0x0, HRSTDISC=B_0x0, HRSTSENT=B_0x0, TXMSGDISC=B_0x0, TXIS=B_0x0
UCPD status register
| TXIS | Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the UCPD_TXDR register. 0 (B_0x0): New Tx data write not required 1 (B_0x1): New Tx data write required |
| TXMSGDISC | Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle. 0 (B_0x0): No Tx message discarded 1 (B_0x1): Tx message discarded |
| TXMSGSENT | Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised. 0 (B_0x0): No Tx message completed 1 (B_0x1): Tx message completed |
| TXMSGABT | Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit. 0 (B_0x0): No transmit message abort 1 (B_0x1): Transmit message abort |
| HRSTDISC | Hard Reset discarded The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit. 0 (B_0x0): No Hard Reset discarded 1 (B_0x1): Hard Reset discarded |
| HRSTSENT | Hard Reset message sent The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit. 0 (B_0x0): No Hard Reset message sent 1 (B_0x1): Hard Reset message sent |
| TXUND | Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit. 0 (B_0x0): No Tx data underrun detected 1 (B_0x1): Tx data underrun detected |
| RXNE | Receive data register not empty detection The flag indicates that the UCPD_RXDR register is not empty. It is automatically cleared upon reading UCPD_RXDR. 0 (B_0x0): Rx data register empty 1 (B_0x1): Rx data register not empty |
| RXORDDET | Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the UCPD_RX_ORDSET register. It is cleared by setting the RXORDDETCF bit. 0 (B_0x0): No ordered set detected 1 (B_0x1): A new ordered set detected |
| RXHRSTDET | Rx Hard Reset receipt detection The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit. 0 (B_0x0): Hard Reset not received 1 (B_0x1): Hard Reset received |
| RXOVR | Rx data overflow detection The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit. The buffer overflow can occur if the received data are not read fast enough. 0 (B_0x0): No overflow 1 (B_0x1): Overflow |
| RXMSGEND | Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message. 0 (B_0x0): No new Rx message received 1 (B_0x1): A new Rx message received |
| RXERR | Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set. 0 (B_0x0): No error detected 1 (B_0x1): Error(s) detected |
| TYPECEVT1 | Type-C voltage level event on CC1 line The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. 0 (B_0x0): No new event 1 (B_0x1): A new Type-C event |
| TYPECEVT2 | Type-C voltage level event on CC2 line The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit. 0 (B_0x0): No new event 1 (B_0x1): A new Type-C event |
| TYPEC_VSTATE_CC1 | The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. 0 (B_0x0): Lowest 1 (B_0x1): Low 2 (B_0x2): High 3 (B_0x3): Highest |
| TYPEC_VSTATE_CC2 | CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value. 0 (B_0x0): Lowest 1 (B_0x1): Low 2 (B_0x2): High 3 (B_0x3): Highest |
| FRSEVT | FRS detection event The flag is cleared by setting the FRSEVTCF bit. 0 (B_0x0): No new event 1 (B_0x1): New FRS receive event occurred |