PA15_PUPEN=B_0x0, nRST_STDBY=B_0x0, WWDG_SW=B_0x0, IO_VDD_HSLV=B_0x0, DUALBANK=B_0x0, BOR_LEV=B_0x0, IWDG_SW=B_0x0, IWDG_STDBY=B_0x0, SWAP_BANK=B_0x0, TZEN=B_0x0, SRAM2_ECC=B_0x0, SRAM2_RST=B_0x0, IWDG_STOP=B_0x0, SRAM1345_RST=B_0x0, nRST_SHDW=B_0x0, nRST_STOP=B_0x0, nBOOT0=B_0x0, SRAM3_ECC=B_0x0, IO_VDDIO2_HSLV=B_0x0, nSWBOOT0=B_0x0, BKPRAM_ECC=B_0x0
FLASH option register
| RDP | Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for more details. 85 (B_0x55): Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) 170 (B_0xAA): Level 0 (readout protection not active) 204 (B_0xCC): Level 2 (chip readout protection active) |
| BOR_LEV | BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset. 0 (B_0x0): BOR level 0 (reset level threshold around 1.7 V) 1 (B_0x1): BOR level 1 (reset level threshold around 2.0 V) 2 (B_0x2): BOR level 2 (reset level threshold around 2.2 V) 3 (B_0x3): BOR level 3 (reset level threshold around 2.5 V) 4 (B_0x4): BOR level 4 (reset level threshold around 2.8 V) |
| nRST_STOP | Reset generation in Stop mode 0 (B_0x0): Reset generated when entering the Stop mode 1 (B_0x1): No reset generated when entering the Stop mode |
| nRST_STDBY | Reset generation in Standby mode 0 (B_0x0): Reset generated when entering the Standby mode 1 (B_0x1): No reset generate when entering the Standby mode |
| nRST_SHDW | Reset generation in Shutdown mode 0 (B_0x0): Reset generated when entering the Shutdown mode 1 (B_0x1): No reset generated when entering the Shutdown mode |
| SRAM1345_RST | SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 0 (B_0x0): SRAM1, SRAM3, SRAM4 and SRAM5 erased when a system reset occurs 1 (B_0x1): SRAM1, SRAM3, SRAM4 and SRAM5 not erased when a system reset occurs |
| IWDG_SW | Independent watchdog selection 0 (B_0x0): Hardware independent watchdog selected 1 (B_0x1): Software independent watchdog selected |
| IWDG_STOP | Independent watchdog counter freeze in Stop mode 0 (B_0x0): Independent watchdog counter frozen in Stop mode 1 (B_0x1): Independent watchdog counter running in Stop mode |
| IWDG_STDBY | Independent watchdog counter freeze in Standby mode 0 (B_0x0): Independent watchdog counter frozen in Standby mode 1 (B_0x1): Independent watchdog counter running in Standby mode |
| WWDG_SW | Window watchdog selection 0 (B_0x0): Hardware window watchdog selected 1 (B_0x1): Software window watchdog selected |
| SWAP_BANK | Swap banks 0 (B_0x0): Bank 1 and bank 2 addresses not swapped 1 (B_0x1): Bank 1 and bank 2 addresses swapped |
| DUALBANK | Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0 (B_0x0): Single bank Flash with contiguous address in bank 1 1 (B_0x1): Dual-bank Flash with contiguous addresses |
| BKPRAM_ECC | Backup RAM ECC detection and correction enable 0 (B_0x0): Backup RAM ECC check enabled 1 (B_0x1): Backup RAM ECC check disabled |
| SRAM3_ECC | SRAM3 ECC detection and correction enable 0 (B_0x0): SRAM3 ECC check enabled 1 (B_0x1): SRAM3 ECC check disabled |
| SRAM2_ECC | SRAM2 ECC detection and correction enable 0 (B_0x0): SRAM2 ECC check enabled 1 (B_0x1): SRAM2 ECC check disabled |
| SRAM2_RST | SRAM2 erase when system reset 0 (B_0x0): SRAM2 erased when a system reset occurs 1 (B_0x1): SRAM2 not erased when a system reset occurs |
| nSWBOOT0 | Software BOOT0 0 (B_0x0): BOOT0 taken from the option bit nBOOT0 1 (B_0x1): BOOT0 taken from PH3/BOOT0 pin |
| nBOOT0 | nBOOT0 option bit 0 (B_0x0): nBOOT0 = 0 1 (B_0x1): nBOOT0 = 1 |
| PA15_PUPEN | PA15 pull-up enable 0 (B_0x0): USB power delivery dead-battery enabled/TDI pull-up deactivated 1 (B_0x1): USB power delivery dead-battery disabled/TDI pull-up activated |
| IO_VDD_HSLV | High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V 0 (B_0x0): High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) 1 (B_0x1): High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) |
| IO_VDDIO2_HSLV | High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V. 0 (B_0x0): High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) 1 (B_0x1): High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) |
| TZEN | Global TrustZone security enable 0 (B_0x0): Global TrustZone security disabled 1 (B_0x1): Global TrustZone security enabled |