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STMicroelectronics /STM32U595 /GTZC2_TZSC /TZSC_SECCFGR1

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Interpret as TZSC_SECCFGR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI3SEC)SPI3SEC 0 (LPUART1SEC)LPUART1SEC 0 (I2C3SEC)I2C3SEC 0 (LPTIM1SEC)LPTIM1SEC 0 (LPTIM3SEC)LPTIM3SEC 0 (LPTIM4SEC)LPTIM4SEC 0 (OPAMPSEC)OPAMPSEC 0 (COMPSEC)COMPSEC 0 (ADC2SEC)ADC2SEC 0 (VREFBUFSEC)VREFBUFSEC 0 (DAC1SEC)DAC1SEC 0 (ADF1SEC)ADF1SEC

Description

TZSC secure configuration register 1

Fields

SPI3SEC

secure access mode for SPI3
LPUART1SEC

secure access mode for LPUART1
I2C3SEC

secure access mode for I2C3
LPTIM1SEC

secure access mode for LPTIM1
LPTIM3SEC

secure access mode for LPTIM3
LPTIM4SEC

secure access mode for LPTIM4
OPAMPSEC

secure access mode for OPAMP
COMPSEC

secure access mode for COMP
ADC2SEC

secure access mode for ADC2
VREFBUFSEC

secure access mode for VREFBUF
DAC1SEC

secure access mode for DAC1
ADF1SEC

secure access mode for ADF1

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data