This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
| XFRC | XFRC |
| CHH | CHH |
| STALL | STALL |
| NAK | NAK |
| ACK | ACK |
| TXERR | TXERR |
| BBERR | BBERR |
| FRMOR | FRMOR |
| DTERR | DTERR |