DSIRST=B_0x0, USBRST=B_0x0, SAI1RST=B_0x0, SAI2RST=B_0x0, TIM17RST=B_0x0, LTDCRST=B_0x0, GFXTIMRST=B_0x0, USART1RST=B_0x0, SPI1RST=B_0x0, TIM15RST=B_0x0, TIM1RST=B_0x0, TIM16RST=B_0x0, TIM8RST=B_0x0
RCC APB2 peripheral reset register
| TIM1RST | TIM1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM1. |
| SPI1RST | SPI1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the SPI1. |
| TIM8RST | TIM8 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM8. |
| USART1RST | USART1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the USART1. |
| TIM15RST | TIM15 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM15. |
| TIM16RST | TIM16 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM16. |
| TIM17RST | TIM17 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the TIM17. |
| SAI1RST | SAI1 reset This bit is set and cleared by software. 0 (B_0x0): No effect 1 (B_0x1): Reset the SAI1. |
| SAI2RST | SAI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the SAI2. |
| USBRST | USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the USB. |
| GFXTIMRST | GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the GFXTIM. |
| LTDCRST | LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the LTDC. |
| DSIRST | DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): No effect 1 (B_0x1): Reset the DSI. |