STMicroelectronics /STM32U595 /RCC /RCC_CCIPR2

MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved

0 (B_0x0): HCLK selected

1 (B_0x1): PLL1 “P” (pll1_p_ck) selected

2 (B_0x2): PLL3 “Q” (pll3_q_ck) selected

3 (B_0x3): input pin AUDIOCLK selected

4 (B_0x4): MSIK clock selected

SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.

0 (B_0x0): PLL2 “P” (pll2_p_ck) selected

1 (B_0x1): PLL3 “P” (pll3_p_ck) selected

2 (B_0x2): PLL1 “P” (pll1_p_ck) selected

3 (B_0x3): input pin AUDIOCLK selected

4 (B_0x4): HSI16 clock selected

SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.

0 (B_0x0): PLL2 “P” (pll2_p_ck) selected

1 (B_0x1): PLL3 “P” (pll3_p_ck) selected

2 (B_0x2): PLL1 “P” (pll1_p_ck) selected

3 (B_0x3): input pin AUDIOCLK selected

4 (B_0x4): HSI16 clock selected

SAES kernel clock source selection This bit is used to select the SAES kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): SHSI selected

1 (B_0x1): SHSI / 2 selected, can be used in range 4

RNG kernel clock source selection These bits are used to select the RNG kernel clock source.

0 (B_0x0): HSI48 selected

1 (B_0x1): HSI48 / 2 selected, can be used in range 4

2 (B_0x2): HSI16 selected

3 (B_0x3): reserved

SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change it only after reset and before enabling the SDMMC.

0 (B_0x0): ICLK clock selected

1 (B_0x1): PLL1 “P” (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)

DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): PLL3 “P” (pll3_p_ck) selected

1 (B_0x1): DSI PHY PLL output selected

USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.

0 (B_0x0): PCLK1 selected

1 (B_0x1): SYSCLK selected

2 (B_0x2): HSI16 selected

3 (B_0x3): LSE selected

LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value.

0 (B_0x0): PLL3 “R” (pll3_r_ck) selected

1 (B_0x1): PLL2 “R” (pll2_r_ck) selected

OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source.

0 (B_0x0): SYSCLK selected

1 (B_0x1): MSIK selected

2 (B_0x2): PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz

3 (B_0x3): PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz

HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.

0 (B_0x0): SYSCLK selected

1 (B_0x1): PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz

2 (B_0x2): PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz

3 (B_0x3): PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz

I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.

0 (B_0x0): PCLK1 selected

1 (B_0x1): SYSCLK selected

2 (B_0x2): HSI16 selected

3 (B_0x3): MSIK selected

I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.

0 (B_0x0): PCLK1 selected

1 (B_0x1): SYSCLK selected

2 (B_0x2): HSI16 selected

3 (B_0x3): MSIK selected

OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.

0 (B_0x0): HSE selected

1 (B_0x1): PLL1 “P” (pll1_q_ck) selected,

2 (B_0x2): HSE/2 selected

3 (B_0x3): PLL1 “P” divided by 2 (pll1_p_ck/2) selected