STMicroelectronics /STM32U595 /RCC /RCC_CFGR2

AHB prescaler This bitfiled is set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Table�118). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided

8 (B_0x8): SYSCLK divided by 2

9 (B_0x9): SYSCLK divided by 4

10 (B_0xA): SYSCLK divided by 8

11 (B_0xB): SYSCLK divided by 16

12 (B_0xC): SYSCLK divided by 64

13 (B_0xD): SYSCLK divided by 128

14 (B_0xE): SYSCLK divided by 256

15 (B_0xF): SYSCLK divided by 512

APB1 prescaler This bitfiled is set and cleared by software to control the division factor of APB1 clock (PCLK1). 0xx: PCLK1 not divided

4 (B_0x4): PCLK1 divided by 2

5 (B_0x5): PCLK1 divided by 4

6 (B_0x6): PCLK1 divided by 8

7 (B_0x7): PCLK1 divided by 16

APB2 prescaler This bitfiled is set and cleared by software to control the division factor of APB2 clock (PCLK2). 0xx: PCLK2 not divided

4 (B_0x4): PCLK2 divided by 2

5 (B_0x5): PCLK2 divided by 4

6 (B_0x6): PCLK2 divided by 8

7 (B_0x7): PCLK2 divided by 16

DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value.

4 (B_0x4): DCLK divided by 2

5 (B_0x5): DCLK divided by 4

6 (B_0x6): DCLK divided by 8

7 (B_0x7): DCLK divided by 16

AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1.

0 (B_0x0): AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1 (B_0x1): AHB1 clock disabled

AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3.

0 (B_0x0): AHB2_1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1 (B_0x1): AHB2_1 clock disabled

AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR2 are off.

0 (B_0x0): AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1 (B_0x1): AHB2_2 clock disabled

APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.

0 (B_0x0): APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1 (B_0x1): APB1 clock disabled

APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all APB2 peripherals clocks are off.

0 (B_0x0): APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits

1 (B_0x1): APB2 clock disabled