PLL1SRC=B_0x0, PLL1QEN=B_0x0, PLL1MBOOST=B_0x0, PLL1M=B_0x0, PLL1REN=B_0x0, PLL1PEN=B_0x0
RCC PLL1 configuration register
| PLL1SRC | PLL1 entry clock source This bitfield is set and cleared by software to select PLL1 clock source. It can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, this bitfield value must be zero. 0 (B_0x0): No clock sent to PLL1 1 (B_0x1): MSIS clock selected as PLL1 clock entry 2 (B_0x2): HSI16 clock selected as PLL1 clock entry 3 (B_0x3): HSE clock selected as PLL1 clock entry |
| PLL1RGE | PLL1 input frequency range This bit is set and reset by software to select the proper reference frequency range used for PLL1. It must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz |
| PLL1FRACEN | PLL1 fractional latch enable This bit is set and reset by software to latch the content of PLL1FRACN in the ΣΔ modulator. In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL initialization phase for details). |
| PLL1M | Prescaler for PLL1 This bitfield is set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). … 0 (B_0x0): division by 1 (bypass) 1 (B_0x1): division by 2 2 (B_0x2): division by 3 15 (B_0xF): division by 16 |
| PLL1MBOOST | Prescaler for EPOD booster input clock This bitfield is set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1�input�clock�frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPODboost mode is disabled (see Section�10: Power control (PWR)). others: reserved 0 (B_0x0): division by 1 (bypass) 1 (B_0x1): division by 2 2 (B_0x2): division by 4 3 (B_0x3): division by 6 4 (B_0x4): division by 8 5 (B_0x5): division by 10 6 (B_0x6): division by 12 7 (B_0x7): division by 14 8 (B_0x8): division by 16 |
| PLL1PEN | PLL1 DIVP divider output enable This bit is set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when pll1_p_ck is not used. 0 (B_0x0): pll1_p_ck output disabled 1 (B_0x1): pll1_p_ck output enabled |
| PLL1QEN | PLL1 DIVQ divider output enable This bit is set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when pll1_q_ck is not used. 0 (B_0x0): pll1_q_ck output disabled 1 (B_0x1): pll1_q_ck output enabled |
| PLL1REN | PLL1 DIVR divider output enable This bit is set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when pll1_r_ck is not used. This bit can be cleared only when the PLL1 is not used as SYSCLK. 0 (B_0x0): pll1_r_ck output disabled 1 (B_0x1): pll1_r_ck output enabled |